1. Field of the Invention
The present invention is related to a method of controlling a refresh operation of PSRAM and related device, and more particularly, to a method of providing refresh collision protection in PSRAM and related device.
2. Description of the Prior Art
Random access memory (RAM) is a form of computer data storage. There are two main types of RAM: static RAM (SRAM) and dynamic RAM (DRAM). In DRAM, memory cells are essentially made up of a transistor and capacitor pair. The capacitor holds a high or low charge, and the transistor acts as a switch to allow the control circuitry on the chip to access or change the capacitor's state. Data are stored in the DRAM memory cells in the form of electric charges which need to be periodically refreshed. In SRAM, memory cells store data using flip-flops which do not need to be refreshed, thereby providing faster access time. However, an SRAM device generally is larger in size and consumes more power than a DRAM device.
A pseudo-static RAM (PSRAM) internally uses a cell structure of DRAM and is externally similar to SRAM, thereby combining the higher density of DRAM with the simpler control of SRAM. Refresh operation is also needed to prevent loss of data stored in memory cells. A PSRAM device includes an internal refresh oscillator to perform a refresh operation at a constant period, and may automatically perform a hidden refresh by using a refresh control pulse generated by the refresh oscillator.
If a read/write command is externally input to the PSRAM device while a memory cell is being refreshed by the internal refresh oscillator, data of the memory cell may not be guaranteed to execute the read/write operation. Therefore, a hidden refresh request which conflicts with an external command is delayed and executed later in the prior art PSRAM device. In order to store the delayed hidden refresh commands, the prior art PSRAM device requires many buffers which may occupy large chip area. Also, a delayed hidden refresh request may cause another conflict with a subsequent hidden refresh request, which further complicates the control of the refresh operation in the prior art PSRAM device.